1. Field of the Invention
The present invention generally relates to a method for forming a cells array of mask read only memory (MROM), and relates to a method which reduces word line resistance and increases process window.
2. Description of the Prior Art
Essential configuration of cells array of conventional mask ROM is shown in FIG. 1 which is a top-view illustration. Numerous word lines 11 crisscross numerous bit lines 12, each word line 11 (bit line 12) is essentially parallel to and insulated to other word lines 11 (bit lines 12) 12. Moreover, one cell 13 of mask ROM is formed by both gate structure, where one word line 11 crosses one bit line 12, and surrounding space. Clearly, whether any cell 13 is opened or closed is decided by how threshold voltage of this cell 13 is adjusted in a code process. Further, in the code process, photoresist is used to cover part of cells which need not to adjust threshold voltage but to expose other part of cells which need to adjust threshold voltage in accordance with data to be stored, then an ion implantation process is performed to implant numerous ions into part of substrate which under gate structures should be adjusted corresponding threshold voltage.
However, owing to limitation of structure of cells 13 (or cells array), some defects of code process will is more serious while scale of mask ROM is continually decreased. Refers to FIG. 2A which is a cross sectional illustration along AA1 and omits both word line and dielectric layer for simplifying illustration, all sources and all drains are formed by numerous doped regions 22 in substrate 21, and gate structures 23 are located on substrate 21. Moreover, while cells array is programmed to store data, code photoresist 24 is used to control which cells are exposed and then ions 25 can be implanted into these uncovered cells, as FIG. 2B shows. Natural, whenever location of photoresist 24 is misaligned, as FIG. 2C shows, part of ions 26 will be implanted into cells that should be not be implanted for adjusting threshold voltage. Thus, because distance between adjacent gate structures is decreased as size of cells, or viewed ad critical dimension of MROM, is decreased, allowable misalignment of photoresist also is proportionally decreased. In other words, process window is decreased, then cost of corresponding fabrication is increased and quality of corresponding products is decreased.
Furthermore, because that lateral scatter of ions in the ions implantation process always is negligible, no matter it is induced by laterally incident ions 27, by scatters of ions induced by gate structure 23 or conductor line 24, or is induced by other unavoidable limitations of practical fabrication. It is indisputable that interference between neighboring cells always is negligible, except while scale of mask ROM cells is continually decreased. Besides, accompany with decrease of critical dimension of MROM, thickness of doped regions for forming both sources and drains also is proportionally decreased and an unavoidable defect is that resistance of doped regions is increased.
Accordingly, conventional structure of cells of mask ROM can not avoid some defects that are more and more serious while scale of cells is continually decreased. Thus, it is desired to develop a new method for forming mask ROM cell to improve fabrication of cells MROM and let MROM can be properly applied in the deep-submicron devices.
One primary object of the invention is to provide a method for forming cells array of mask read only memory ROM.
Another object of the invention is to provide a method for decreasing word line resistance and increasing process window during fabrication of MROM.
Still an object of the invention is to provide a cells array of MROM, which is suitable for deep-submicron products, without obvious modification of conventional fabrication of MROM.
Essential flow of the invention at least includes: form numerous gate structures on substrate; form numerous doped regions in uncovered part of substrate; form first conductor layer on uncovered part of substrate with a thickness essentially equal to thickness of gate structures; form first dielectric layer on first conductor layer; form second conductor layer on both gate structures and first dielectric layer; perform a pattern transform process for transferring both second conductor layer and gate structures into conductor lines as word lines; form second dielectric layer on sidewalls of conductor lines to form spacer; form code photoresist on second conductor layer; and perform ions implantation process for implant numerous ions into partial substrate which is not covered by code photoresist.